| http://www.w3.org/ns/prov#value | - The clock period width is 400nS and last 32 cycle with every 52.4ms repeated. 2.5 Miscellaneous Signal Name Type Pin No. /RST I 45 REF_CLK I 47 DAISY_IN I/PU 51 O/ML 52 MDO O 43 MDC /TEST O I/PD 42 44 DAISY_OUT Description Reset : Active Low The chip is reset when this signal is asserted Low Reference clock : The input is a c
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