| http://www.w3.org/ns/prov#value | - FIG. 17A is a block diagram of an integrated circuit including a random access memory, RAM, in an intellectual property core and a test port; FIG. 17B is a state diagram describing testing procedures for the RAM; and FIG. 17C is a block diagram of an integrated circuit including plural embedded RAMs in an intellectual property core and a test port.
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