About: http://webisa.webdatacommons.org/85942833

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	Thus, AND gate 42b has one input at logic 0 and one input at logic 1 (which could be called a disable signal to the output line 21ob of the ROM 21) so that the output AND gate 42b is a logic 0 which is inputted to OR gate 43b.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com