| http://www.w3.org/ns/prov#value | - FIG. 2 is a circuit schematic of a single CAM cell portion of a CAM word shown in FIG. 1, wherein the bit lines and compare lines are multiplexed onto the CAM cell depending on whether the CAM cell is undergoing a read/write or compare operation, and wherein the exclusive NOR compare circuitry can be selectively disabled during the read/write operation to minimize power consumption;
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