| http://www.w3.org/ns/prov#value | - FIG. 9B is a circuit diagram showing the D flip flop configured based on the basic cells of FIG. 9A. In FIG. 9B, the terminals 25 and 27 are connected to each other in the basic cells of FIG. 9A. Further, the nodes 20 and 22 are connected to the gates of the p-channel TFT 13 and the n-channel TFT 16, respectively.
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