About: http://webisa.webdatacommons.org/88233884

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 3 is a circuit schematic of a logic inversion gate of the type embodying the present invention driving an output buffer circuit constructed in accordance with prior U.S. Pat. No. 5,465,054 to provide a full-range output signal.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com.au