| http://www.w3.org/ns/prov#value | - In switching from time period 3 to time period 4, control circuit 205 in processor 201 opens register write buffer 116 in switching pipeline processes from (EXP1) to (WB1) and, as a result, one of the processing results is transmitted from data processing unit output bus 125 to general register 106 in processor 201 via the opened register write buffer 116.
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