| http://www.w3.org/ns/prov#value | - ch shows a state in which a gate electrode pad is arranged at a corner of the chip and FIG. 6 is a plan view showing a portion of a chip which shows a state in which a gate electrode pad is arranged in the midst of a side of the chip. [0052] In the embodiment 1, an example in which the present invention is applied to a vertical type power transistor (semiconductor device) 1 is explained.
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