| http://www.w3.org/ns/prov#value | - FIG. 1B is a circuit diagram illustrative of a first delay circuit provided in a conventional clock generator circuit having a phase lock loop of FIG. 1A. The first delay circuit 7 comprises a resistor R1 connected in series between the input and output sides, and a capacitor C1 connected between a ground line and the output side of the first delay circuit 7.
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