| http://www.w3.org/ns/prov#value | - outputs said first latch signal as a first cascade signal; and a second bit section including a second latch portion which outputs a second latch signal, and including an AND gate which takes a logical AND of said first cascade signal inputted to one terminal thereof and said second latch signal inputted to another terminal thereof, and which outputs an AND signal as a second bit signal. 8.
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