About: http://webisa.webdatacommons.org/97746841

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	If it is determined that the write operation is a cache miss cycle, address strobe signal MADS is asserted on the system bus by a cache controller during bus state 102.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com