| http://www.w3.org/ns/prov#value | - The inventive concept of the FPMCA chip 30 of the invention is the inclusion of a programmable address decoder 32 (see FIG. 5) and programmable interconnect 34 (see FIG. 8) that allow selective reconfiguration of the sea of N memory cells 36 (see FIG. 3) of the FPMCA chip 30 to N???1 bit, N/2???2 bits, N/4???4 bits or in general, N/k???k bits, where k is a power of two.
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