| http://www.w3.org/ns/prov#value | - As one of known methods to solve these problems, there is a method in which the reference clock signal CK1 is inputted to the multiplexer 13 at a delay time of Td by a delay device 14, and in which the reference clock signal CK1 is divided by 1/m by a frequency divider 15 before the divided reference clock signal CK1 is inputted to the data output unit 11 as a data request signal.
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