| http://www.w3.org/ns/prov#value | - FIG. 4 is a bit map of typical read and write packets addressed to a device such as the one in FIG. 3 and shows how the packet frame structure of the IEEE protocol shown in FIG. 2 could be modified to accommodate the multiple-register-access mode of the present invention, assuming that all thirty-two registers are accessed in a multiple register access cycle.
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