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xsdhhttp://www.w3.org/2001/XMLSchema#
Subject Item
isa:49767802
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prov:value
controller means including means for determining the average system bus latency, and means responsive to said determined average system bus latency for assigning locations inside said random access memory to have at least one logical FIFO for storing data, the size of said logical FIFO being related to said determined average system bus latency; and network DMA controller means coupled to said at
prov:wasQuotedFrom
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