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An Entity of Type : prov:Entity, within Data Space : webisa.webdatacommons.org associated with source dataset(s)

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  • As shown in FIG. 1 and FIG. 2, when a processor unit (CPU0) requests an access to a memory, the access request to the memory is broadcast to all the system controllers (SC0, SC1)that are relevant to the access, in order to maintain the coherence between cache devices.
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