| http://www.w3.org/ns/prov#value | - ing said clock to said bit stream, characterized in that said apparatus comprises: a preamble detection circuit, for detecting reception of said preamble pattern responsive to receipt of n bits of said pattern, where n is an integer, an n<m; n<k+1, and means for disabling said means for synchronizing until said preamble detection circuit has detected said preamble pattern, and wherein said preambl
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