| http://www.w3.org/ns/prov#value | - The device of claim 4, wherein said multi-queue FIFO memory chip is configured to support queue switch operations having N cycles of latency, where N is a positive integer greater than one; and wherein said multi-queue FIFO memory chip is further configured so that the read pointer associated with the first one of the plurality of FIFO queues is automatically decremented by a value in a range from
|
