| http://www.w3.org/ns/prov#value | - FIG. 7C is an example of the inverse timing signal HT3 in this case, which is a signal that inverts every 1H. In this case, the inverse timing signal HT3 may be a signal of reverse phase to the signal shown in FIG. 7. [0130] In the case of this example, the clock signal CLK is generated based on the horizontal sync signal S4 as a reference signal in the PLL circuit 152.
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