| http://www.w3.org/ns/prov#value | - The TFTs 5 and 6 of the array are then completed by forming a gate insulating layer on the channels, gate electrodes on the gate insulating layer, source and drain regions, and any other required layers for a functional TFT, as shown in FIG. 4D. If desired, a second interlevel insulating layer 3C is formed over the second device level 2B.
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