| http://www.w3.org/ns/prov#value | - 2N vertically arranged logic blocks, where N is an integer greater than two; a first interconnect line originating substantially at a 1st logic block at the top of the first column, programmably coupling the 1st logic block to an N+1st logic block, and extending into a substantially identical lower column located below the first column to programmably couple to the 1st logic block in the lower col
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