| http://www.w3.org/ns/prov#value | - As a result of this, the voltage Vo at the output terminal 11 rapidly rises to reach to the high level H at the instant t1 ', as shown in FIG. 2D. In this case, since the MOS FET 6 is not turned off as long as the first input signal V1 takes levels other than a level almost equal to the low level L, there is little an overlapping period between the falling portion of the first input signal V1 and
|
