| http://www.w3.org/ns/prov#value | - s ???L???, that is, the ground potential Vss, and the output signal RDECADS of the row address decoder RADD2 also indicates ???L???, that is, the ground potential Vss. [0223] Therefore, in the operation other than the erase operation, the signal line 22 (FIG. 8) provided on the memory cell array in the unselected memory cell block is set to the ground potential Vss, the select gate lines SG1, SG2
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