| http://www.w3.org/ns/prov#value | - Specifically, FIG. 29 shows a top view of an exemplary construction 700 comprising a substrate having a memory array region 14 (diagrammatically illustrated as a box bounded by dashed line 708), a region 18 peripheral to the memory array where logic or other circuitry can be formed (diagrammatically illustrated as a box bounded by dashed line 704), and a region 16 between the memory array region 1
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