| http://www.w3.org/ns/prov#value | - In a microprocessor having an internal data bus of n bytes, where n is greater than 2, said microprocessor for providing address signals or an n byte transfer of data and for receiving a ready signal when external memory is ready to transfer data, said microprocessor also including a cache memory, an improvement is said microprocessor comprising:a first input means for receiving at least one byte
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