| http://www.w3.org/ns/prov#value | - BRIEF DESCRIPTION OF THE DRAWINGS [0011]FIG. 1 is a diagram illustrating a portion of a memory-cell array in a conventional DRAM. [0012]FIG. 2 is a functional block diagram of a memory system including a memory controller and a memory device including a self-refresh controller according to one embodiment of the present invention. [0013]FIGS. 3A and 3B are diagrams illustrating signals generated by
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