| http://www.w3.org/ns/prov#value | - The TFTs 5 and 6 of the array are then completed by forming a gate insulating layer on the channels, gate electrodes on the gate insulating layer, source and drain regions, and any other required layers for a functional TFT, as shown in FIG. 4B. Alternatively, the step of forming a mask 31 and the step of disabling the TFTs 6 by etching or ion implantation may be carried out after the first and th
|
