| http://www.w3.org/ns/prov#value | - The upstream portion of the memory bus 706, referred to as the upstream bus, returns requested read data and/or error, status or other operational information, and this information may be forwarded to the subsequent memory module(s) 710 via bypass circuitry; be received, interpreted and re-driven if it is determined to be targeting an upstream memory module 710 and/or memory controller 704 in the
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