| http://www.w3.org/ns/prov#value | - The system defined in claim 8, wherein said digital encoder comprises:a memory for storing C samples successively written therein at successive addresses thereof; memory control means having said sampling signal frequency 4fcc, said phasing signal ?? and said control signals G1, G2, RIQ, and BLS applied thereto (1) for permitting every 2nth C sample (where n is a given integer) occurring from the
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