| http://www.w3.org/ns/prov#value | - Memory controller 26 produces a control signal such as a write pulse or read pulse to be applied to memory element 24 by using control signals such as write enable, read enable and timing signals applied from memory control signal producing unit 25 and the signal ACT. Memory controller applies control signals to memory element 24 to perform one of a plurality of access operations to enable data D0
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