| http://www.w3.org/ns/prov#value | - g circuits of the type shown in FIG. 11 to reduce the potential for race through in accordance with an embodiment of the present invention.FIG. 13 is a diagram of a clock tree that may be used on an integrated circuit such as a programmable logic device integrated circuit to distribute clock signals in accordance with an embodiment of the present invention.FIG. 14 is a diagram of a clock driver ci
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