| http://www.w3.org/ns/prov#value | - The system of claim 21 wherein the bus master means includes means for setting the Valid, Exclusive, and Written bits in the second location to 1, 0, and 0, respectively, if the first state represents a condition in the third location wherein the written bit equals a 1 and the request is a read request or the first state represents a condition the Valid, Exclusive, and Written bits in the
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